In this project, you will implement a simple digital notch (or comb) filter, using input from an analog-to-digital converter (ADC) module and producing output through a digital-to-analog converter (DAC). You will test the frequency response with a sine wave generator and an oscilloscope.
The conceptual design is fairly simple, as shown below. The two main components are a fixed length delay, whose length is equal to the period of the filter's fundamental freqency, and a subtraction unit. The filter output Y(n) is the difference between the current value of X(n) and the output of the delay:
Y(n) = X(n) - X(n - delay)
A typical filter response is shown to the right. The first "notch" corresponds to the fundamental frequency of the filter, and there are additional notches at each higher harmonic of that frequency
The project uses the peripheral ADC and DAC modules PMOD_AD1 and PMOD_DA1.As a starting point, pre-made VHDL control interfaces for both of these modules (pmod_da1_ctrl.vhd and pmod_ad1_read.vhd) are available for download from the course web page. Data sheets for the modules are also available in PDF form).The block diagram above shows a suggested structure for designing the notch filter, with the user-provided parts on the left, and the provided I/P and external PMOD modules on the right.
The main functionality of the user design is in the functional block labeled "Buffer and ADC/DAC controller". The two main functions of this block are:
The pipeline delay buffer and digital filter output need to be updated once per ADC sample, so the timing of the buffer and ADC/DAC controller block can be synchronized with (or driven by) the combined DONE signal from the two PMOD controller blocks.
Since the resolution of the filter is limited by the 8-bit DAC resolution, it is only necessary to keep and use the 8 most significant bits of the ADC reading.
For example, if the DAC_clk is 1/16 of the 100 MHz oscillator clock, the ADC sample rate will be around 300-350 kHz, depending on the exact controller design. With a RAM depth of 4096 (12 address bits), the lowest possible fundamental frequency setting would be slightly below 100Hz.
Make sure that the address offset setting has the same number of bits as the RAM address ports, and that it is set by a corresponding number of user switches on the BASYS 3 board.
The DAC has two independent output channels. We recommend that one channel is used for the filter output, while the other channel outputs a copy of the current ADC input. This allows the filter input and output to be directly compared with an oscilloscope.
You will therefore need to perform the calculation so that the final answer is compatible with the DAC output. Hint: the center of the 0-255 scale is 128).
To avoid this issue, logic-derived signals can be converted to globally-available timing signals through the use of dedicated clock buffers. These can be configured and generated with the Clocking Wizard in the IP Catalog, or instantiated directly in VHDL. See the Lecture 5 notes for more information.
You will also need a function generator to produce a sine wave input for the filter. Before connecting the function generator output to the ADC module, connect it directly to the oscilloscope and adjust the amplitude and offset to create a sine wave with range between 0 and 3.3V.
Connect the two DAC output(s) to channels 1 and 2 of the oscilloscope, and set the delay switches to select a fundamental filter frequency in the ~few kHz range. By varying function generator frequency, confirm that the output amplitude of the notch filter goes to zero at that frequency, as well as integer multiples (harmonics) of the fundamental frequency.
Change the pipeline buffer delay to a different value and verify that the "notch" frequencies in the filter response change accordingly, as expected.
Show your code and results to the instructor.