Lab 5

Design of a UART receiver


In this lab you will design the receiver part of a simple UART, that is designed to receive one data byte at a time at 9600 Baud with no parity and one stop bit.

The background for this project may be found in the Lecture 7 slides on this website.


A proposed design for your UART receiver would include:

Simulating your design

Simulate the design in Vivado. Your test bench stimulus should produce a valid RS232 data frame with correct 9600 baud timing. The simulation clock frequency should match the 100 MHz board clock on the BASYS3.

Implementing the design

After you have sucessfully simulated the UART receiver, implement it on the Basys3 developer board. Choose one of the available PMOD ports for the RS232 interface module, and assign the appropriate I/O pins in your user constraints.

Connect the RS232 interface module to your computer's serial port through the provided null modem cable. Open a terminal and type "minicom" from the command line for a text-based serial terminal emulator. You may ask the instructor for help configuring and using Minicom

From Minicom, you can transmit individual characters to the UART receiver, and verify that the correct ASCII values of those characters are correctly received.