Lab 4: Digital Stopwatch

Block Diagram


In this lab you will design a one-button stopwatch with start, stop and reset functions.

The background for this project may be found in the Lecture 6 slides on this website.


This is a more "advanced" assignment in this course, in which you should use your understanding of VHDL and FPGA design to produce a design that is both well-structured and works correctly.

You are free to choose your own approach. That said, a typical stopwatch design will include the following elements:

More about "Press Detect"

The press buttons on the Basys2 developer boards have capacitors in parallel with them, so they do not "bounce" when pressed. So no debounce logic (covered in Lecture 6) is needed. But it is important to start the stopwatch state machine at the start of the button press (even if the button is held for a long time).

There are multiple ways to do this, and you are encouraged to try out your own ideas. One possible approach is a state machine that reads the button value at each 100 Hz clock cycle. Such machine would need at least two states:

Notice that this approach produces a button_press signal that lasts for exactly one 100 Hz clock cycle (10 ms).

Testing your design

After simulating the design, implement it and download it to the Basys3 developer board. Print out the code for your final design and hand it in to the instructor.