Lab 8

Digital notch filter

Introduction

In this project, you will implement a simple digital notch (or comb) filter, using input from an analog-to-digital converter (ADC) module and producing output through a digital-to-analog converter (DAC). You will test the frequency response with a sine wave generator and an oscilloscope.

The conceptual design is fairly simple, as shown below. The two main components are a fixed length delay, whose length is equal to the period of the filter's fundamental freqency, and a subtraction unit. The filter output Y(n) is the difference between the current value of X(n) and the output of the delay:

Y(n) = X(n) - X(n - delay)

A typical filter response is shown to the right. The first "notch" corresponds to the fundamental frequency of the filter, and there are additional notches at each higher harmonic of that frequency

Design overview

The project uses the peripheral ADC and DAC modules PMOD_AD1 and PMOD_DA1.As a starting point, pre-made VHDL control interfaces for both of these modules (pmod_da1_ctrl.vhd and pmod_ad1_read.vhd) are available for download from the course web page. Data sheets for the modules are also available in PDF form).

The block diagram above shows a suggested structure for designing the notch filter, with the user-provided parts on the left, and the provided I/P and external PMOD modules on the right.

The main functionality of the user design is in the functional block labeled "Buffer and ADC/DAC controller". The two main functions of this block are:

Fixed-length delay buffer controller: This part is similar to the pipelined buffer design in lab 3. In this block, use a local counter to provide read and write addresses to the two respective ports of the dual-port RAM. The offset between the read and write addresses is set by switches, so that the fundamental frequency of the filter can be user-adjusted.
ADC/DAC driver: For each filter cycle, the ADC needs to digitize a new data sample, and the DAC must set a new level for the analog output. The ADC and DAC controllers can be run in parallel, and both are initialized by setting the "rst" signal to '1' and then back to '0'. Both controllers set their respective "DONE" outputs to '1' when the read/write operations are complete and they are ready to start again.

The ADC and DAC controllers are not able to run at the 100 MHz system clock rate, so a clock divider is necessary to produce a slower serial clock for those modules. This clock can be produced by a counter-based clock divider, or a clock management tile configured and generated from IP Catalog.

The pipeline delay buffer and digital filter output need to be updated once per ADC sample, so the timing of the buffer and ADC/DAC controller block can be synchronized with (or driven by) the combined DONE signal from the two PMOD controller blocks.

Implementaton details

The following are some additional details and clarifications for implementing the design:

Data formats

The ADC controller module pmod_ad1_read.vhd has two analog voltage inputs channels (0 and 1) produces two corresponding 12-bit outputs in unsigned form, one for each channel. The DAC controller module pmod_da1_ctrl.vhd has two analog output channels (0 and 1), set by two corresponding 8-bit unsigned outputs.

Since the resolution of the filter is limited by the 8-bit DAC resolution, it is only necessary to keep and use the 8 most significant bits of the ADC reading.

Pipeline buffer

The input and output data widths of the dual-port RAM block should be 8 bits, to match the filter output resolution. The depth of the RAM (number of addresses) should be long enough to accommodate a wide range of fundamental frequencies.

For example, if the DAC_clk is 1/16 of the 100 MHz oscillator clock, the ADC sample rate will be around 300-350 kHz, depending on the exact controller design. With a RAM depth of 4096 (12 address bits), the lowest possible fundamental frequency setting would be slightly below 100Hz.

Make sure that the address offset setting has the same number of bits as the RAM address ports, and that it is set by a corresponding number of user switches on the BASYS 3 board.

Inputs and outputs

The ADC module has two input channels, of which only one is needed for the design. You can choose either input and ignore the other one.

The DAC has two independent output channels. We recommend that one channel is used for the filter output, while the other channel outputs a copy of the current ADC input. This allows the filter input and output to be directly compared with an oscilloscope.

Filter algorithm

In the final stage of the filter, the delay buffer output is subtracted from the latest ADC sample. Subtracting two arbitrary unsigned 8-bit numbers can give a result anywhere between -255 and +255 (9 bits). But the output to DAC must be an 8-bit unsigned number (0-255).

You will therefore need to perform the calculation so that the final answer is compatible with the DAC output. Hint: the center of the 0-255 scale is 128).

Derived clocks

The PMOD modules and ADC/DAC controller modules are driven by a divided 100MHz clock, and the main buffer/ADC/DAC controller state machine needs to operate from an even slower clock derived from the DONE results of those modules. Driving flip-flops from logic derived signals (aka "gated clocks") can give poor timing performance and warnings from Vivado.

To avoid this issue, logic-derived signals can be converted to globally-available timing signals through the use of dedicated clock buffers. These can be configured and generated with the Clocking Wizard in the IP Catalog, or instantiated directly in VHDL. See the Lecture 5 notes for more information.

Implementing and testing the design

The top level design should receive the 100 MHz on-board oscillator clock and user-switches for setting the pipeline buffer length. The PMOD DA1 and AD1 modules can be plugged into two PMOD ports of your choice; consult the BASYS3 user manual to find the corresponding I/O pins for SCK, SD0, SD1 and SYNC/CS on each of the boards.

You will also need a function generator to produce a sine wave input for the filter. Before connecting the function generator output to the ADC module, connect it directly to the oscilloscope and adjust the amplitude and offset to create a sine wave with range between 0 and 3.3V.

Connect the two DAC output(s) to channels 1 and 2 of the oscilloscope, and set the delay switches to select a fundamental filter frequency in the ~few kHz range. By varying function generator frequency, confirm that the output amplitude of the notch filter goes to zero at that frequency, as well as integer multiples (harmonics) of the fundamental frequency.

Change the pipeline buffer delay to a different value and verify that the "notch" frequencies in the filter response change accordingly, as expected.

Show your code and results to the instructor.