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Schema HT2020

Lectures

lecture 1 (Recommended reading: Chapter 1 of textbook, see Resources below)

lecture 2 (Recommended reading: Chapters 2-4)

lecture 3 (Recommended reading: Chapters 5 and 7)

lecture 4

lecture 5

lecture 6

lecture 7

Lab exercises

Required

• 1: Combinatorial logic and FPGA design in Vivado

• 2: Sequential logic (serial adder)

• 3: PRNG and programmable data delay

• 4: Digital Stopwatch

Electives

• 5: UART receiver in FPGA

• 6: Simple microprocessor in VHDL

• 7: Arbitrary function generator

• 8: Digital notch filter

Additional exercises (optional)

• Circuit board design (PDF)
  

• Microcontroller tutorial (PDF)
  Supporting documents for the microcontroller lab are here
  

Resources

Downloadable version of course text (Free Range VHDL)

Virtual machine: centos7 image with Vivado installation (centos_vivado.vdi.gz)
This is a 22GB gzip file that expands to 40GB. Run from VirtualBox, with suggested minimum 4GB RAM allocated.

VHDL test bench template (vhdl_tb_blank.vhd)

Four-digit 7-segment hex display (disp4.vhd)

BASYS3 FPGA board manual

PMOD-AD1 ADC module

• Module documentation (PDF)

• PMOD_AD1 readout controller (pmod_ad1_read.vhd)